关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法——改进型时钟脉冲细分技术。
A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
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