任意相位时钟管理器可以产生高精度动态相位的时钟信号。
Arbitrary phase clock management devices can produce high-precision dynamic phase of the clock signal.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
本文介绍了时钟网络中抖动、相位噪声、偏移、频率稳定度等参数的概念以及它们之间的转换关系。
The paper introduce the concepts of timing parameters, including: jitter, phase noise, skew, frequency stabilization, and the relationship between them.
分析了应用于时钟恢复电路中的相位插值器。
In this paper, a detailed analysis of a phase interpolator for clock recovery is presented.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The delay circuit is used for both frequency and phase adjustments of the output clock.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
协议能有效解决数据边界识别问题和时钟累积误差造成的相位偏差问题。
The communication protocol could solve the issue of identifying the data boundaries and the phase error caused by the accumulated error of clock.
输出时钟抖动定义为三种类型：周期抖动，占空比抖动和相位抖动。
Output jitter is defined in three ways: period jitter. duty-cycle jitter, and phase jitter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
写时钟能够生成等间隔初相和初相中间的相位。
The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases.
本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法——改进型时钟脉冲细分技术。
A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper.
补偿器包括控制为输出选择哪个写时钟相位的相位旋转器。
The compensator includes a phase rotator that controls which write clock phase is selected for output.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
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