本文提出了产生数字电路测试码的一种算法——主路径敏化法。
This paper presents an algorithm of test patterns generation for digital circuits which is called the principal path sensitization method.
本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
证明了在任何组合电路中，只需两个测试码便能测试出所有可能的初级输入与输出端之间的短路故障。
It is shown that any feedback bridging faults between primary inputs and the primary output in any general combinational networks can be betected by using only two test patterns.
从工程应用的角度出发，同步时序电路故障模拟采用单测试码故障并行的模拟结果更能反映实际情况。
Presented and implemented in this paper is a fanout source based fault parallelism fault simulator for synchronous sequential circuits.
从工程应用的角度出发，同步时序电路故障模拟采用单测试码故障并行的模拟结果更能反映实际情况。
Presented and implemented in this paper is a fanout source based fault parallelism fault simulator for synchronous sequential circuits.
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