该法被称为1999年集成电路布图设计法。
This Act may be cited as the Layout-Designs of Integrated Circuits Act 1999.
在集成电路布图设计中，通道布线是其关键算法之一。
In the layout of LSI chips, channel routing is one of the key problems.
该法被称为《2000年半导体集成电路布图设计法》。
This Act may be called the Semiconductor Integrated Circuits Layout-Design Act, 2000.
集成电路布图设计是知识产权的重要客体，其技术水准关乎一国信息产业的荣辱兴衰。
The layout design of integrated circuit is an important object of intellectual property right, and its technological level concerns the rise and fall of a nation's information industry.
1999年集成电路布图设计法由新加坡知识产权局颁布，自1999年1月26日起开始实施。
This Act is promulgated by Intellectual Property Office of Singapore, and the date of entry into force is January 26, 1999.
由于集成电路布图设计具有的特殊特征，对它采取何种知识产权的保护方法也在理论界引发了分歧。
Therefore, how to protect the intellectual property of layout-design of integrated circuits has been the matter of concern within intellectual property Law field for several years.
我国的知识产权边境保护措施应当包括专利权、地理标志，不宜将集成电路布图设计纳入保护范围。
The border protection of intellectual rights in China shall include patent right and geography marks, but not the chart of integrate circuit.
作者研究一个在IBMPC/XT型微型计算机上实现的计算机辅助电路布图设计系统。提出了电路布图设计的数学模型；
This paper deals with a Computer aided design system for circuit layout and presents a mathematical model of circuit layout design and its implementation on IBM PC/XT.
受保护的布图设计、有该布图设计的集成电路或者含有该集成电路的物品投入商业利用。
Putting into commercial exploitation of a protected layout-design, integrated circuit incorporating a layout-design or article incorporating an integrated circuit.
两层通道布线问题在超大规模集成电路自动布图设计中是关键步骤之一。
Two-layer channel routing is one of the key steps in the automatic layout design of VLSI chips.
采用标准单元方法的集成电路设计系统是一个用于专用集成电路(ASIC)设计的自动布图系统。
This IC design system applicable to the standard cell method is an automatic layout system used for designing Application Specific ICs (ASIC).
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
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