样机电路划分为发射电路和接收电路两部分。
The prototype circuit includes two parts including launching and receiving circuit.
提出了一种基于F M算法的启发式电路划分新方法。
A new heuristic circuit partitioning approach based on F-M algorithm is presented in this paper.
电路划分是降低超大规模集成电路设计复杂性的有效方法。
VLSI partitioning is an effective method for reducing complexity of VLSI circuit design.
光学测棒硬件控制电路划分为：LED驱动电路、单片机控制、按键触发和数据通信四个功能模块。
The control circuit of the probe has been divided into four modules, namely, infrared LED drive circuit module, monolithic processor control module, keys trigger module and data communication module.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
在明确了系统级的总体规划以及设计层次的划分以后，我们从系统的最底层开始进行数字逻辑电路的设计。
After the system-level spec and the division of the design hierarchy are comfimed, we start to design the digital logic circuit from the bottom for the pixel machine .
因此，如何划分电路，成为电路并行算法的设计基础和成功的关键。
Therefore, how to partition circuit becomes a key to the design base and success.
本文对芯片工作原理、系统架构设计、模块划分、前端模拟电路实现、版图设计等进行了详细分析。
In this thesis, we illustratre the theory of the chip, system design, partition of the modules, simulation and realization of analog circuit and layout design.
其次依照方案中组成单元的划分，详细论述了母板，功能选择与控制电路，模块电路的开发及设计。
Secondly, in accordance with the scheme, the thesis discusses the development and design of the motherboard, function choice and control circuits and module circuits.
校正电路的每个像素的累计使用数据划分成多个数据部分，每个数据部分存储于不同的存储工具。
Accumulated usage data of each pixel of the correction circuit is divided into a plurality of data portions, each of which is stored in a different storing means.
本文运用故障树分析法对模拟电路进行分析，按照电路结构对其按树枝形逐级划分建立故障集；
Fault tree analysis for analyzing analog circuits structure is proposed in this paper, in which fault sets are established according to tree architecture.
完成了发射机数字基带部分模块的功能划分、性能分析与电路设计。
Then we divide the UHF Transmitter into several functional sub-modules, based upon side of which we analyze each sub-modules'performance and accomplish the design of their required circuits.
采用两两相关的方法对电路内部节点的相关性进行建模，并且对相关性进行划分强弱分别进行处理，从而提高了计算的精度。
This paper takes the pair wise correlation model and deals with strong and weak correlation types differently to improve the accuracy of the computation.
将表示电路的超图转化成带权值的无向图，从而将电路二等分问题转化成图的划分问题。
The hypergraph denoting circuit is transformed into a weighted undirected graph, so the problem of circuit bisection is transformed into the graph partition problem.
媒体处理系统结构根据其实现方式的不同，可划分为两种体系结构：专用集成电路媒体处理系统芯片和可编程媒体处理系统芯片。
The architecture of media processing SoC could be failed into two classes based on its implementation method: ASIC's and programmable ones.
然后，根据模块划分设计了基于FPGA的核心控制卡电路板，实现一个具有调度、线路收发、存储、网络管理等功能的基本核心控制卡系统。
This design includes design of a FPGA based Core Control System, which can achieve communication channels transmit and receive, packet storage etc.
将建议方案用于ITC’02基准电路典型芯核的测试链平衡划分。
The proposed technique is applied to the typical cores of ITC'02 SoC benchmarks.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
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