提出了一种全新的电荷泵锁相环的行为级建模方法。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文研究了电荷泵锁相环电路的模型和电路设计。
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
非常适合于电荷泵锁相环（CPPLL）的系统级设计和前期验证。
So the formula is very adapt to the systematic design and early verification of 3 rd Order CPPLL.
电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。
Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.
通过对锁相环原理进行深入的分析和研究，本论文针对CD MA无线通信标准，设计出了高速低功耗三阶电流型电荷泵锁相环。
In this thesis, a high-speed, low-power and third-order current-mode charge-pump PLL is designed according to the CDMA standard by in-depth analyzing and researching the principle of PLL.
文章在深入分析电荷泵锁相环设计理论的基础上，根据DSP芯片对锁相环的具体应用要求，确定了锁相环的总体电路结构和各项性能参数。
Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed.
同时，建立了电荷泵锁相环频率合成器噪声模型，为高阶、低噪声电荷泵锁相环频率合成器的设计提供理论依据。
The noise model CPPLL frequency synthesizer is also established in order to provide theory of designing high order, low noise and high performance CPPLL frequency synthesizer.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
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