电路采用可编程电容阵列，可快速调谐，以保证模块稳定。
In this circuit, programmable capacitor arrays were used to rapidly tune parameters, which ensured stability of the module.
目标频率由一组分立的亚波段组成，通过电容阵列来控制。
The desired frequency is tuning is accomplished by discrete tuning curve among a group of frequency sub-bands through capacitor array.
仿真结果表明，采用5位数控方式调谐电容阵列，调谐时间误差不超过三个时钟周期，满足系统要求。
Simulation results showed that, with 5 CNC mode tuning capacitor arrays, the tuning time error was no more than three clock cycles, which meets requirements of the system.
通过优化集成电感的设计，同时采用NMOS管和开关电容阵列作为可变电容，使该设计具有较低的相位噪声和较宽的调谐范围。
Through inductor optimization, the VCO has a low phase noise and a wide tuning range with switched capacitor array and NMOS varactor.
光子撞击电容器阵列，产生与其强度成正比的电荷，而电荷耦合器又将它转换成电压。
Photons of light striking an array of capacitors create an electrical charge proportional to their intensity, which the charge-coupler transforms into voltage.
这些电容在逐次逼近结构中构成二进制权阵列。
These capacitors form binary weight array in successive approximation architecture.
通孔盘状及平面阵列陶瓷多层电容器焊料所含的铅。
Lead in solders for the soldering to machined through hole discoidal and planar array ceramic multilayer capacitors.
D/A转换器的设计过程中，主要从精度和速度两个方面做分析，对单位电容和开关阵列进行了设计优化。
The unit capacitor and the switch array are optimized so that the DAC can achieve a better tradeoff between accuracy and speed.
本文提出了一种基于流动成像技术测量两相流离散相浓度的新方法。该法以阵列式电容传感器为信息获取手段。
Based on flow imaging technique, a new method for the discrete phase concentration measurement of two phase flow using capacitance array sensor is proposed.
介绍了电容层析成像系统的基本原理和电容敏感阵列结构及其数学模型。
This paper mainly introduces the basic principle about electrical capacitance tomography (ect) system, and describes the structure and mathematic model of the capacitance sensing array.
该传感器阵列(130)使用电容式测量和射频测量中的至少一种从图案(155)收集数据。
The sensor array (130) collects data from a pattern (155) using at least one of a capacitive measurement and a radio frequency measurement.
为了提高电容式触觉传感阵列的性能，本工作以SOI材料中异质结界面作为深槽腐蚀中腐蚀自停止界面，以提高硅膜片的表面平整度和厚度均匀性。
In order to improve the uniformity of the thin film of silicon, the interface of hetero-junction of SOI material was used as the interface of etch self-stopping.
结果，较低有效位和校正位或者校正电容器有可能驻留在子阵列中。
As a consequence the bits of lower significance and the correction bits or correction capacitors are likely to reside in a sub array.
本文首先以平行板阵列电极电容传感器为例对多相界面的检测机理进行了讨论。
This paper first presents a case study dealing with the detection mechanism of multi phase interface level taking a parallel plate capacitance sensor as an example.
本文首先以平行板阵列电极电容传感器为例对多相界面的检测机理进行了讨论。
This paper first presents a case study dealing with the detection mechanism of multi phase interface level taking a parallel plate capacitance sensor as an example.
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