然后，它生成一个报告，列出这些代码单元每个获得了多少个“节拍(tick)”(即当代码的特定单元正在运行时发生了多少次系统时钟中断)。
Then it generates a report that lists how many "ticks" each of these units of code received (how many times a system-clock interrupt occurred when that particular unit of code was running).
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
时钟信号总是由设备端生成的。
并使用时钟测试来减少生成测试向量所需的时间。
It can reduce the time used to generate the test vectors by using the clock test.
写时钟能够生成等间隔初相和初相中间的相位。
The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
FPTA只记录时钟值的整数部分，而用时钟序的概念来模拟表示时钟值小数部分的大小关系，从而减少生成的状态空间。
To reduce the state space, FPTA records the integer values of clocks together with the order of decimal fraction instead of the real number values.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
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