所以环路滤波器的噪声分析非常重要。
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
并提出了从环路带宽和相位余量出发设计环路滤波器的方法。
The method of designing the loop filter with the phase margin and loop bandwidth is displayed.
另一个因素可能是高q值作为我的环路滤波器的更多的宽带噪声。
Another factor could be the high Q of my loop acting as a filter for more broad band noise.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
当PFD在锁定模式中不生成脉冲时，电荷泵不提供电荷给环路滤波器。
When the PFD does not generate pulses in lock mode, the charge pump does not provide charge to the loop filter.
HDPLL中定时误差检测器、环路滤波器是全数字的，而VCXO使用了模拟器件。
The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components.
本文先介绍了锁相环的工作原理，环路滤波器的设计并对相位噪声的理论进行了阐述。
In this article, PLL theory, design of loop filter and phase noise theory are introduced at first.
环路滤波器的作用就是滤除从PFD&CP出来的电压中的高频成分，从而纯化VCO的输出信号。
The function of a loop filter is to filter high-frequency signal out of the output voltage from PFD and CP, thus the output signal from VCO will be purified.
然后分析了现有视频解码系统和环路滤波器设计，并且指出了本设计的重点和难点以及解决的思路。
The commonly used techniques for video systems and loop-filtering are discussed. The author presents a solution and the key points.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
基于低功耗设计考虑，调制器采用有源-无源混合型环路滤波器，并通过离散时间微分技术移除信号求和模块。
Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.
介绍低相噪NPLL频率综合器的设计及实验结果。提出用无源环路滤波器比用有源环路滤波器更好，可获得低相噪设计。
This paper gives the design and experimental results of low noise NPLL frequency synthesizer and concludes that the passive loop filter is more suitable for low noise design than active loop filter.
对锁相环的环路滤波器的设计方法进行了深入研究，给出了一种环路滤波器设计方法，该设计方法与现有设计方法相比具有较明显的优点。
The paper analyzes the design method of passive loop filter thoroughly, and presents a effective design method. The method has obvious advantage comparing to the design method in existence.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
最后针对定时调整算法，研究了插值等式、多项式插值滤波器及插值控制，模拟了插值环路的性能。
Thirdly, interpolation equation, polynomial interpolation filter and interpolation control for timing adjustment are studied. The performance of interpolation loop is simulated.
提出了一种新颖的利用负反馈环路以及RC滤波器提高电源抑制比的高精密CMOS带隙基准电压源。
In this paper, a novel high precision CMOS bandgap voltage reference which USES a negative back circuit and a rc filter to enhance the PSRR is proposed.
文中对自调谐滤波器环路进行了简单地分析。
第四章介绍了在具体的设计中是如何来设计定时同步环路的内插滤波器以及环路的各个部分的。
The fourth chapter will show you the details of the designs in the timing recovery system based on interpolator.
第四章介绍了在具体的设计中是如何来设计定时同步环路的内插滤波器以及环路的各个部分的。
The fourth chapter will show you the details of the designs in the timing recovery system based on interpolator.
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