提出了一种可以进行列主元选取的细粒度lu分解流水线算法并在现场编程门阵列(FPGA)上得到了实现。
This paper presents a fine-grained pipeline algorithm for lu decomposition with column partial pivoting and gives the description of its implementation on field-programmable gate arrays (FPGA).
参与“蓝脑计划”的科学家用一台能同时处理数百万个算法和数据串的“超级计算机”，来实现该过程的流水线工作。
The scientists working on the Blue Brain Project use a “super computer”, a machine capable of handling millions of algorithms and data strings at once, to streamline this process.
实验结果表明，该算法有效地减少了送入图形流水线的几何数据，并在贴地漫游的情况下，显著提高了场景绘制速度。
The experimental results demonstrate that the method reduces the geometry sent to the graphics pipeline and improves the rendering frame rate significantly when navigating at ground level.
采用流水线结构的硬件实现表明，新算法占用的资源大约为原来的1/16。
The pipelined implementation shows that the new algorithm occupies about 1/16 of the old one.
可编程图形处理器允许用户编写运行在其上的顶点着色程序与片断着色程序，取代内置的固定功能渲染流水线，实现定制的渲染算法。
The programmable GPU permits developers to write vertex shaders and fragment shaders running on it, to replace the fixed function pipeline, and to employ custom rendering algorithms.
分析了数学形态学的位移运算，结合TMS320C32DSP的流水线操作和I/O并发模式完成了形态学的快速算法。
The displacement operation for mathematical morphology is analyzed . Combined the streamlined operation of TMS320C32 DSP with I/O concurrent mode, a fast algorithm for morphology is carried out.
改进的任务分配与负载平衡策略，避免了节点机负载的不平衡和流水线作业的积压，提高了算法的效率。
The improved task distribution and load balancing strategy avoid imbalance load on computing nodes and job jam in pipeline, and improve the efficiency of the algorithm.
数值实验结果表明交替平面数据通信策略和块流水线并行算法是有效且可扩展的。
Numerical results have shown that the alternation plane data communication strategy and block pipeline parallel method applied are effective and scalable.
核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。
The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).
同时，为了配合提出的校准算法，在流水线ADC工作模式中加入校准模式。
To fit the presented algorithmic, a calibration mode has been added into the pipeline ADC.
主要讨论了红外序列图像中缓动点目标的流水线检测算法。
This paper focuses on a pipeline algorithm for detecting slowly moving targets in infrared sequence images with complex background.
利用FPGA在硬件上实现了该算法，内部采用流水线技术，校正系数存储在FPGA的片内存储器中并实现了盲元补偿。
In the FPGA design, the pipelined technique is applied and the correction coefficient is stored in the interior memory of FPGA, meanwhile, blind pixel compensation is implemented.
该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。
A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.
文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。
This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.
软件采用了适于流水线运算的块匹配算法，实现了对目标的快速定位和实时跟踪。
The system software uses a block match algorithm easy to flow computing and implements fast detecting and real-time tracking of the moving object.
本文的设计着重从多个层次利用并行处理技术来提高环路滤波的速度，包括流水线设计、数据流驱动控制策略以及算法并行性设计。
Our design emphasizes on using parallel processing technology from multi-level to improve speed, including pipelining design, data-flow drive strategy and algorithmic parallelism design.
基于流水线技术和并行技术的硬件设计保证了该算法的实时实现。
Based on pipeline and parallelism technology, the processor can run in real-time.
图像处理模块实现中值滤波和边缘检测两种算法，在这两种算法的硬件实现中采用了流水线处理技术，显著提高了处理速度。
In image processing module, we design hardware circuits for median filtering and edge detection. The pipelined processing methods are used in circuit design to raise processing speed.
在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基- 4算法，分级流水线以及定点运算结构。
Based on the analysis of the complexity and hardware architecture of FFT, the proposed processor adopts radix-4 DIF algorithm, pipelined architecture and fixed-point operation.
本文分析了常用对称密码算法DES、3des和AES的可重构性，利用流水线、并行处理和可重构技术，提出了一种可重构体系结构。
In this paper, based on the analysis about the reconfiguration of the DES, 3des and AES, we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, par.
本文提出了异步流水线环的一种排队网络近似分析算法。
This paper presents a queueing network approximate analysis method to evaluate the performance of self-timed rings.
改进了DCT变换算法，设计了并行查找表结构的乘法器，采用了流水线优化算法来解决时间并行性问题，提高了DCT模块的运算速度。
Design an multiplication based on parallel LUT (Look up Table). The problem of time parallel is resolved with pipeline optimization algorithm, the speed of DCT is accelerated.
用分块流水线方法设计了超紧致差分格式的并行算法，进行数值实验及并行性能分析。
We examine the super compact symmetric finite difference scheme (SCSFD) and compare it with traditional difference methods and compact difference methods.
流水线结构的CORDIC算法，可以大大提高运算速度。
The pipelined version of CORDIC algorithm can be adopted to achieve greater computing speed.
数值实验结果表明交替平面数据通信策略和块流水线并行算法是有效且可扩展的。
This paper gives the paradigm of alternation plane data communication strategy based on split method in 3D computin.
针对遗传算法软件实现速度慢、效率低的缺点，提出了便于算法实现的串行和流水线两种硬件实现方案。
To overcome the shortcoming of low speed and low efficiency of genetic algorithm's software implementation, two hardware implementation schemes of serial and pipelining realization are put forward.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
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