讨论了简化的四象限乘法器的原理。
The principle of simplified four-quadrant multiplier was discussed.
实践表明，这是一种实用的数字乘法器。
本文简要介绍了几种结构的数字乘法器。
This paper presents briefly the digital multiplier with different structure.
该加法器可以实现两输入的光学算术运算。
This adder can realize the optical arithmetic operation with two inputs.
减法器(16)从读取信号中减去所述串扰信号。
A subtractor (16) subtracts the crosstalk signal from a read signal.
与传统的移位乘法器相比，它将乘法器速度提高一倍。
Compared with the traditional serial multiplier, it can obtain twice speed-up.
所用的方法是，将相加两数的各位同步地输入到加法器中。
The concept used is that the bits of the two numbers to be added are made available to the adder synchronously.
实验结果表明流水线加法器的速度高于其它结构实现的加法器。
The result of experiment indicates that the pipeline adder is faster others.
本文给出一种任意多位的保留进位阵列乘法器的自动设计方法。
This paper presents an automatic design method for a carry save array multiplier with arbitrary number of bits.
介绍了用FPGA实现先行进位单元阵列除法器的原理及方法。
The theory and method of precedent cellular arrays divider by means of FPGA are introduced.
一个简单的加法器描述，以前在别的网站上被发过，现在存在这里。
A simple adder described previously in other websites have been made, and now exist here.
乘法器将所述减法结果乘以十六进制数‘10’，产生第一临时变量；
The multiplier multiply said results with 10 of hexadecimal to produce No. 1 variable.
结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
It shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
根据平行并行乘法器，设计了适用于模乘运算的一维阵列组合乘法器。
The one-array combinative multiplication was designed on the basis of the parallel multiplication.
本论文研究的主要内容是有限域算术、椭圆曲线加密算法和有限域乘法器。
The finite field arithmetic, elliptic curve cryptography (ECC) and the finite field multiplier are investigated in this thesis.
根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。
A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
讨论了基于MOS晶体管亚阈值区特性的CMOS四象限模拟乘法器的设计。
The design technique for a CMOS four quadrant analog multiplier is presented, which is based on the characteristics of the MOSFET subthreshold region.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。
The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.
什么？你也知道他？芬丹从他那拿到了进行某种仪式的一件法器。这是女皇的最后希望。
What? You know him as well? He gave Findan an artifact for a rite. It is her last hope.
复数加法运算复杂，用硬件实现复数加法，需要使用数目众多的加法器，占用大量的面积。
Operation of plurality add is very complicated. In the design will numerous adders be used and large area will be consumed.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
此压缩器已作为一个压缩模块，用在32位浮点乘法器的软核设计中，得到了很好的结果。
The compressor has been used in the IP software core design of 32bits floating multiplier as a module, and acquire a good result.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
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