出于教学的目的，让我们在一个银行相关环境中研究触发器，在该模拟环境中，我们仅仅建立了一张表。
For educational purposes, let's study triggers in the context of a bank that has a simple setup of just one table.
一个或多个数字信号处理器(DSP)耦合起来可以构成速度很快的模拟-数字转换器(asc)，用来执行信号获取、预处理、触发器生成等操作。
One or more digital signal processors (DSPs) coupled to fast analog-digital converters (ADCs) perform the signal acquisition and pre-processing, trigger generation, and so forth.
本文介绍了一种通过增加触发器来模拟主外键，实现级联更新功能的方法。
The article shows one solution that we add triggers to simulate the primary key and foreign key, and then realize cascade update.
最后用计算机模拟程序检验绝热触发器和可变计数电路的结果。
Finally, Computer simulation has shown that above flip-flop and adiabatic variable counter are stable with lower power consumption.
它由与输入控制电压同步的触发器控制四模拟开关阵列的开关转换来选择输出极性。
Its output polarity is determined by the four analog switch array controlled by an input-synchronized trigger.
它由与输入控制电压同步的触发器控制四模拟开关阵列的开关转换来选择输出极性。
Its output polarity is determined by the four analog switch array controlled by an input - synchronized trigger.
提出以电流信号表示逻辑值的新型低噪声触发器设计，用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。
Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
标记有两种状态，而且是一个触发器的软件模拟。
The SR Flip-Flop is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates.
分析和应用表明，数字式触发器优于模拟式触发器。
Thus, the digital trigistor is formed. From analysis and ap…
分析和应用表明，数字式触发器优于模拟式触发器。
Thus, the digital trigistor is formed. From analysis and ap…
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