设计师马腾·巴斯编成1美刀iPhone应用程序的实时模拟数字时钟，本来是一个博物馆的作品。
Designer Maarten Baas adapted his Real Time Analog Digital Clock, originally a museum piece, into a one dollar iPhone app.
第二天，当程序员用终端模拟窗口再次打开应用服务器和数据库服务器时，她向下看了一眼Windows任务栏中的时钟。
Later that day, when she had terminal emulation Windows opened against the application server and database server, the programmer looked down at the clock on the Windows taskbar.
这是一个多语种的发言时钟使用超过50种不同的皮肤，以显示时间，您使用的不是数字或模拟显示器。
This is a multilingual Speaking Clock that uses over 50 different skins to show the time to you using either digital or analogue displays.
操作时钟时采用了模拟时序的方式而不是常规的中断方式。
Operation of the clock timing used in the simulation of the way rather than the interruption of conventional methods.
时钟同步和载波同步是接收机的关键问题，传统模拟解调可靠性、稳定性差，调试复杂。
Time synchronization and carrier synchronization are cruxes of receiver. The reliability and stability of traditional analog demodulation are bad, and adjustment is complex.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
但这还不是全部，它也支持文本到语音和MS代理，使您的计算机更有趣，同时拥有一个具有数字和模拟时钟面临多种选择全图形显示。
But that's not all, it also supports text-to-speech and MS Agents to make your computer more fun and also features a fully graphical display with several options of digital and analog clock faces.
实时时钟模块提供的是分为模拟和数字域名。
The real time clock module provides is divided into an analog and a digital domain.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
实验和模拟结果均表明：采用简化方案时转换输出的伪归零信号所包含的时钟分量的强度小于采用抽运探测方案的情况。
Both of them shows that the clock component contained in the converted PRZ signal obtained using the simplified scheme is weaker than that using the pump-probe scheme.
FPTA只记录时钟值的整数部分，而用时钟序的概念来模拟表示时钟值小数部分的大小关系，从而减少生成的状态空间。
To reduce the state space, FPTA records the integer values of clocks together with the order of decimal fraction instead of the real number values.
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
将复合视频、YC分量等模拟视频信号进行AD转换以获取图像的数字信号，同时提取其中的同步和时钟信号。
The composite video, YC component analog video signals such as AD conversion to obtain digital image signals, to extract the synchronization and clock signals. (2) Embedded Systems PCB drawing.
设计方案的优劣依赖于精确到时钟周期级别的微体系结构模拟器评估。
To evaluate the design alternatives, Micro-architects rely on the cycle level micro-architecture simulators.
数字式时钟渐渐取代了模拟的机械时钟而成为人们日常生活的必需品之一，对人们的生活提供很大帮助。
Digital clock gradually replaced the simulation of mechanical clock and become one of people's Daily life necessities to people's life and provide great help.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
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