通过对二元关系核运算性质的研究，定义出任何一个二元关系的商集。
Through study on Rernel operation nature of duality relation, the definition of quotient set for every duality relation was presented.
IPN250结合了一个GT240 96核心CUDAGPU，英特尔酷睿2.26GHz双核处理器和8G DDR3 SDRAM，可以提供每卡高达390GFLOPS的运算性能。
The IPN250 combines a single GT240 96-core CUDA GPU with an Intel Core2 Duo host processor operating at 2.26GHz and 8 GBytes of DDR3 SDRAM to deliver up to 390 GFLOPS of performance per card slot.
RS编码器IP核设计的难点是提高编码电路的编码运算速度。
The difficulty of RS encoder IP core design is how to improve operation rate of encoding circuit.
针对基于核密度估计的图像互信息估计法运算量很大的问题，提出了一种快速互信息估计算法。
A new fast algorithm was presented to accelerate the computation of mutual information of images based on kernel density estimate.
文章在进行循环移位运算的算法和性能分析的基础上，对循环移位器IP软核与硬核的设计作了详细阐述。
This paper discusses the design of hard and soft IP core of cycling shifter particularly on basement of analyzing the arithmetic and capability of cycling shift operation.
设计了只有一个图像和一个灰度结构核的单通道非相干光学相关器来并行一步取阈完成击中与否运算。
Then a single channel incoherent optical correlator with only an image and a structural element is developed to execute the hit miss transform in parallel by one step thresholding.
研究设计了一种具有自主知识产权的高速、高精度的有限域多项式相乘运算核。
In this thesis, the design and FPGA implementation result of a finite field polynomial multiplier is presented, whose arithmetic architecture is based on the number theoretic transform.
本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。
This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.
对IP核所采用的结构、卷积运算的硬件实现进行研究。
The structure of IP core and the hardware implementation of convolution were investigated.
对IP核所采用的结构、卷积运算的硬件实现进行研究。
The structure of IP core and the hardware implementation of convolution were investigated.
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