传统晶体管使用一个叫做“栅极”的金属电极,以控制电子在平面硅基片上的沟道中的流动。
Conventional transistors use a metal electrode, called the gate, to control the flow of electrons through a planar channel in the silicon substrate.
以及一电压提升装置,用以控制该第一MOS晶体管及该第二MOS晶体管的栅极;
The voltage lifting device controls grid electrodes of the first MOS transistor and the second MOS transistor.
解决上述问题的方法是自动控制输出电路MOS管的栅极电压变化率。
This problem can be solved by controlling the variety speed of the G-S(grid-source) voltage of MOS transistors.
将通道外伸、三面围以栅极原子,这样就能够增加栅极的表面积,更好地控制通道,并减少泄漏。
By sticking the channel into the air and surrounding it on three sides with the atoms of the gate, you increase the surface area of the gate.
本文描述了用于装配电子枪时控制阴极与第一栅极间距的光纤传感器的结构及其测量系统。
The construction and measurement system of fiber-optic sensor for monitoring the distance between cathode and first grid during assembly of electron gun are described.
在给定晶体管中的第一栅极导体和第二栅极导体的相对尺寸控制晶体管的阈值电压。
The relative sizes of the first and second gate conductors in a given transistor control the threshold voltage for the transistor.
本文提出了一种电子的栅极控制线路,可用来控制高压离子变流装置的工作。
An electronic circuit which may be applied to the control of firing Angle of high voltage mercury arc current converter is suggested in this paper.
半导体装置包括从基底突出的隔离层、分隔件、隧道绝缘层、浮置栅极、介电层图案和控制栅极。
The semiconductor device includes a isolated layer protruding from a substrate, a separator, a tunnel insulation layer, a floating grid, a dielectric layer pattern and a control grid.
它采用了绝缘栅极双极型二极管和电压型换流器,控制和运行方式简单,输出波形好,具有广阔的应用范围和良好的发展前景。
It can be widely used for its easy and simple control and operation as well as for its good output waveforms.
如此形成的晶体管的阈值电压由保持在浮动栅极上的电荷量控制。
The threshold voltage of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate.
多条字线连接到具有NAND单元阵列结构且布置在相同行中的单位元件的控制栅极。
Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows.
多条字线连接到具有NAND单元阵列结构且布置在相同行中的单位元件的控制栅极。
Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows.
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