最后，文章还对伪流水线型时间数字转换器各级子时间数字转换器进行了优化。
Finally, the paper illustrates the detailed structure of the sub-time-to-digital converter in each stage.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
FPGA中有着丰富的资源，目前已经有很多基于FPGA实现时间数字转换电路的研究工作。
There are many resources in FPGA. There are many works about using the resources of FPGA to realize time-to-digital converter circuits.
本论文在调研了以前时间数字转换电路工作的基础上，对用FPGA中的专用进位连线来实现时间数字转换电路的研究进行了全面详细的介绍。
Based on the survey of previous works, we put forward and introduce our method of realizing precise time-to-digital converter circuits by using the dedicated carry chain of FPGA.
本论文在调研了以前时间数字转换电路工作的基础上，对用FPGA中的专用进位连线来实现时间数字转换电路的研究进行了全面详细的介绍。
Based on the survey of previous works, we put forward and introduce our method of realizing precise time-to-digital converter circuits by using the dedicated carry chain of FPGA.
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