通过实践表明，本文设计的时钟采样帧发生器IP核可靠易用，可扩展功能强，满足了实际应用系统的技术要求。
Having been applied in practical project, the result indicates that the IP core is reliable, powerfully extensible. It has satisfied technical target of real system.
一般采样脉冲都是在装置内部时钟的控制下产生的。
Generally sampling pulse is produced by the control of clock inner device.
把所述自适应滤波器（15）和减法器（16）与异步时钟（18）耦合以便以异步采样率操作。
The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate.
同时发现各线路间传输延迟有半个周期的不一致，因此在接收端应把采样时钟上升沿调整在所有解出数据都稳定的时刻。
So the synchronous parellel data can be gotten if the rising of sample clock is set at the middle of the stable time of all deserialized data.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution.
该技术通过消除采样开关有限导通电阻的影响，补偿了采样带宽，并避免了时钟馈通和电荷注入的加剧。
The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
研究了传感器、执行器为时钟驱动，控制器为事件驱动，网络诱导时延大于一个采样周期的网络(ncs)的稳定性问题。
This paper discusses the stability of NCS with time-delay longer than one sampling period when both sensor and actuator are time-driven as well as controller is event-driven.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
在时钟电路中采用分相采样技术，实现了定时分析最高200m的等效采样速率。
Application of the technology of sampling in different phase in clock circuit realizes maximum 200m equivalent sampling rate of timing analyzer.
为了能在异步控制网络上实现采样同步，可采用时钟同步方法。
Using the clock synchronization, synchronous sampling could be realized on an asynchronous control network.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
提出基于频相的直接数字频率合成技术（DDFS）实现采样的跟随时钟。
Offering direct digital frequency synthesis (DDFS) based on the frequency -phase to achieve the following sampling clock.
在发送端时钟频率随时间变化的情况下，以较低的成本和较简单的电路实现，保证了接收端采样数据及音频数据恢复的准确性。
Because clocking frequency of sending terminal is changed with times at lower cost and simple circuit, accuracy of receiving end sampled data and audio - data recovery is assured.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
它包括高速随机振荡信号发生器、交错停振控制单元、时钟发生器和采样单元。
The low power consumption digital true random source comprises a high speed random oscillator signal generator, an alternative oscillation stop control unit, a clock generator and a sampling unit.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
选用GN-80型GPS接收设备和单片微机进行电力系统状态变量同步采集终端的硬件设计，利用GPS的精确授时作为其同步时钟控制采样脉冲来实现同步采样。
This thesis selects model GN-80 GPS receiver and SCM to design the sampling device. The high accurate time service is used to synchronize the sample clock signal to realize synchronous sampling.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
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