许多设计需要FIFO弹性缓冲器，在不同时钟速率的次系统和通道的需求中形成桥梁。
Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements.
在这篇文章中，他摒弃了一直误导着人们的观念，那就是摩尔定律将继续促进越来越高的CPU时钟速率。
In it, he tore apart the misplaced belief that Moore's Law would continue to unleash higher and higher CPU clock speeds.
我们设计的电路板要支持更多的功能、更高的时钟速率和更低的电压，这就要求有更多的功率和更高的电流。
We designed the circuit board to support multifunctionality, higher clock speeds and lower voltages, which requires more power and higher current.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
据认为，用大脑里所谓的内置时钟——用相对规范的速率来衡量事物——计算时间。
Brains were thought to measure time by using some kind of internal clock that generates events at a relatively regular rate.
游戏在快速的硬件下不会有问题，但就像第一个解决方案，你浪费了太多的时钟周期，这本来能提供更高的帧速率。
The game will have no problems on fast hardware, but like the first solution, you are wasting so many precious clock cycles that can be used for a higher framerate.
一个好的经验法则是在32位CPU上以每字节10个CPU时钟周期的速率加密。
A good rule of thumb is to encrypt on a 32-bit CPU at the rate of 10 CPU clock cycles per byte.
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
可是人人皆知，尽管时钟和地球自转是规则的，我们对时间的体验却有不同的速率。
Everybody has noticed that, despite clocks and the regular turning of the earth, time is experienced as passing at different rates.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
特别说明了该声码器根据外部提供的同步时钟自适应地改变工作速率的方法。
Especialy realized the method of adapting to change its work rate in accordance with outward provided synchronization clock.
在时钟电路中采用分相采样技术，实现了定时分析最高200m的等效采样速率。
Application of the technology of sampling in different phase in clock circuit realizes maximum 200m equivalent sampling rate of timing analyzer.
还请注意，因为没有参考时钟，帧速率。
Please also notice that because there is no reference clock, the frame rate.
更高速率系统的研制目前也在开展中。时钟恢复电路(CRC)是光纤通信和许多类似数字通信领域中不可缺少的关键电路。
Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
数据传输FIFO的，地点为发送时钟使用的传输速率地址指针在发送时钟速度递增。
Data is transmitted out of the FIFO at a transmit clock rate using a transmit address pointer incremented at the transmit clock rate.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
获取时钟相对于实际时间的当前前进速率。
Gets the rate at which the clock's time is currently progressing, compared to real-world time.
获取时钟相对于实际时间的当前前进速率。
Gets the rate at which the clock's time is currently progressing, compared to real-world time.
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