采用一个单时钟输入来控制所有内部转换周期。
A single clock input is used to control all internal conversion cycles.
采用一个单端时钟输入来控制所有内部转换周期。
A single-ended clock input is used to control all internal conversion cycles.
(增加)外部的时钟是通常的解决方案，但这要求数字源设备具有时钟输入接口。
An external clock is a common solution but it requires a digital source equipped with clock input, it exists but it is rare and specific.
初看上去，也许会考虑使用动作管脚（管脚12）从一个计数器接到第二个计数器的时钟输入管脚（管脚14），简单的级联两个计数器。
At first blush, you might think that you could simply cascade two counters together using the carry-out pin, Pin 12, from one counter to feed the clock-input pin, Pin 14, of a second counter.
不支持12小时时钟，也不支持输入月和日。
There's no support for 12-hour clocks, or for just entering month and day.
另一个例子是设计从内部时钟获取数据的系统，用来取代请求用户输入。
Another example is designing a system that gets the date from the internal clock instead of asking for input from users.
我的问题是，我怎么知道输入时钟频率应该是多少？
My question is, how do I know what the input CLK frequency should be?
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。
Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device.
这将作为外部时钟的输入端。
我读过的数据表，但找不到任何参考指定一个输入时钟频率。
I've read the datasheet but can't find any reference to specifying an input CLK frequency.
在时钟界面下方提供恋人输入最想说的一句话，让另一半时刻温馨在自己的柔情中。
Interface below the clock input to provide the most would like to say a word lover, so the other half in their tender moment in the warmth.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
程序可以启动查找文件，如果用户开始输入，程序可以放弃，直到下一次空闲时钟周期。
The application can launch a search for a file, and if the user begins typing, merely abandon it until the next hiatus.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
数据读取连续的驱动ic的输入时钟的上升沿一旦机顶盒输入线变低。
Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.
你可以输入持续时间和时钟时间。
在串行数据输入（DI）或输出（DO）时使用的时钟信号。
Used as the synchronization clock when inputting (DI) or outputting (DO)serial data.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
可以提供输入及输出用于引入及输出精确参考时钟信号。
Inputs and outputs are provided for bringing in and outputting precision reference clock signals.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
其也可由参考输入时钟的较大的抖动引起。
It can also be caused by excessive jitter on the REFCLK input.
时钟等快速开关信号必须利用数字地屏蔽起来，以免向电路板上的其它器件辐射噪声，并且绝不应靠近基准输入。
Fast switching signals, such as clocks, must be shielded with digital ground to avoid radiating noise to other parts of the board, and must never be run near the reference inputs.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
能用键盘输入的方法修改电子时钟的时间。
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
输入时钟频率为500hz，灯亮的时间在1—4秒之间，可以自由控制。
Input clock frequency of 500hz, the time for lights between 1-4 seconds, they can control.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
全系统采用输入数据的同步时钟作为系统时钟，系统内部采用全并行的方式，以提供灵活的速度。
The system use input clock as system clock and use parallel structure in system to provide flexible speed.
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