如果您没有将工作平台上的时钟和所有在测系统上的时钟进行同步，那么报告中的资源计数器将显示不准确(就时间而论)。
If you do not synchronize the clocks on the workbench and on all of the systems under test, resource counters are displayed inaccurately (with respect to time) in the reports.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
时钟或者选通信号用于比较器、递增-递减计数器102和数模转换器100的同步操作，以便避免这些部件竞争。
A clock or a strobe signal is used to synchronise operation of the comparator, the up-down counter 102 and the digital to analog converter 100 so as to avoid these components racing.
的变化，反映在时序安排的40103向下计数器，必须喂以较低利率计数时钟，这并不影响产出率的PWM波的列车。
The change is reflected in the clocking arrangements of the 40103 down-counter, that must be fed with a lower rate counting clock.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
计数器是最常用的时序电路之一，他们不只可以用来指望脉冲，还可以分频，定时，发生跳动的脉搏和其他的时钟信号等。
The counter is the most commonly used one of the sequential circuits, they not only can be used to count on pulse, still can separate frequency, timing, produce beats pulse and other clock signal etc.
初看上去，也许会考虑使用动作管脚（管脚12）从一个计数器接到第二个计数器的时钟输入管脚（管脚14），简单的级联两个计数器。
At first blush, you might think that you could simply cascade two counters together using the carry-out pin, Pin 12, from one counter to feed the clock-input pin, Pin 14, of a second counter.
我们采用基于时钟的粗计数器来量化被测时间间隔中与时钟同步的部分；
The time-interval could be divided into two parts, namely clock synchronized part and clock unsynchronized part.
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
应用推荐