在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。

To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.

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每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。

Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.

youdao

每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。

Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.

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