每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
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