时钟脉冲，用于同步的连续脉冲信号串。
CLOCK SIGNAL, a continuous string of pulses used for synchronization.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
但是，新型基站利用GPS，可充分发挥卫星发射的高精度时钟脉冲。
But new cell stations use GPS to take advantage of the highly accurate clock pulses transmitted by satellites.
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法——改进型时钟脉冲细分技术。
A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
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