外部设备——例如，通用串行总线(usb)端口或系统时钟。

External devices — For instance, Universal Serial Bus (USB) ports or the system clock.

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本设计方案描述了为不同宽度读写数据端口的数据宽度转换，怎样基于FPGA的FIFO实现共有时钟(同步)。

This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports.

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它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。

It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.

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端口时钟被分频为所需的频率或被保持在其原始频率。

The port clock is divided to a desired frequency or kept at its original frequency.

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设计人员总把SRAM作为其最基本的形式，即单端口、单时钟域器件。

Designers traditionally think of SRAM in its most basic form, a single-ported, single-clock domain device.

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设计人员总把SRAM作为其最基本的形式，即单端口、单时钟域器件。

Designers traditionally think of SRAM in its most basic form, a single-ported, single-clock domain device.

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