窗口是在客户端时钟和服务器时钟之间所允许的最大偏差。
The window is the maximum allowable drift between the client clock and the server clock.
这将作为外部时钟的输入端。
时钟信号总是由设备端生成的。
同时发现各线路间传输延迟有半个周期的不一致，因此在接收端应把采样时钟上升沿调整在所有解出数据都稳定的时刻。
So the synchronous parellel data can be gotten if the rising of sample clock is set at the middle of the stable time of all deserialized data.
文中还提出了用偏振全息术获得多输出端时钟分布的方案。
Methods for obtaining multiple fan out clock distribution using polarization holographic technique is also proposed.
这样，就在接收端所在的时钟域中造成了亚稳态。
Whenever this happens, there is a possibility of meta-stability in the receiving clock domain.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
初步实验得到了可作为4输出端时钟分布的全息光学元件。
Polarization holographic technique was adopted to fabricate the HOEs. 4 fan out clock distribution has been obtained in primary experiments.
采用一个单端时钟输入来控制所有内部转换周期。
A single-ended clock input is used to control all internal conversion cycles.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。
Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.
在发送端时钟频率随时间变化的情况下，以较低的成本和较简单的电路实现，保证了接收端采样数据及音频数据恢复的准确性。
Because clocking frequency of sending terminal is changed with times at lower cost and simple circuit, accuracy of receiving end sampled data and audio - data recovery is assured.
时间服务将不再同步，并且无法向其他客户端提供时间或更新系统时钟。
The time service is no longer synchronized and cannot provide the time to other clients or update the system clock.
时钟信号输入端被设计用于提供时钟信号。
它提供一个数据时钟输出(DCO)用于在输出端捕获数据，以及一个帧时钟输出(FCO)用于发送新输出字节信号。
A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided.
管理员正在配置sso令牌配置策略的时钟容差，想要定义客户端和域控时钟之间的时间斜公差。
An administrator is configuring the clock tolerance for the Single Sign-On token configuration policy and wants to define the time skew tolerance between a client and the domain controller clock.
管理员正在配置sso令牌配置策略的时钟容差，想要定义客户端和域控时钟之间的时间斜公差。
An administrator is configuring the clock tolerance for the Single Sign-On token configuration policy and wants to define the time skew tolerance between a client and the domain controller clock.
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