补偿器包括控制为输出选择哪个写时钟相位的相位旋转器。
The compensator includes a phase rotator that controls which write clock phase is selected for output.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
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