该比较器包含一级预放大器、动态锁存器及时钟控制反相器。
The comparator includes a preamplifier, a dynamic latch and a clocked inverter.
每个看门狗具有一个可选择的预分频器(从1到64K)，可用于时钟看门狗定时器也能触发dma请求和捕获比较通道。
Each watchdog has a selectable prescaler (from 1 to 64 k) that can be used to clock the watchdog timers which can also trigger DMA requests and capture compare channels.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
时钟或者选通信号用于比较器、递增-递减计数器102和数模转换器100的同步操作，以便避免这些部件竞争。
A clock or a strobe signal is used to synchronise operation of the comparator, the up-down counter 102 and the digital to analog converter 100 so as to avoid these components racing.
频率比较器比较基准时钟和输出时钟的频率，并输出频率比较信号。
A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
最后在考虑实际因素的基础上，依次设计了时钟产生电路、前置滤波器、带隙基准源、开关电容积分器、锁存比较器和DAC等子模块电路并做了仿真。
The factors which will be encountered are descried and modules include anti-aliasing filter, clock circuit, band gap voltage reference, sc integrator, latched comparator and DAC are designed.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
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