本文通过对NRZ、RZ伪随机码序列进行频谱分析，得知当NRZ码变换成码元占空比为1/2的RZ码时，所提取出的定时时钟功率最强。
By analysing frequency spectrum in this paper, we can understand that when NRZ code be transferred into RZ code of 1/2 mark-to-space ratio, the timing clock can be obtained at largest power.
我们设计的电路板要支持更多的功能、更高的时钟速率和更低的电压，这就要求有更多的功率和更高的电流。
We designed the circuit board to support multifunctionality, higher clock speeds and lower voltages, which requires more power and higher current.
一粒被连接到一个或多个时钟域并连接到至少一个电源域，并且包括定义的信号和用于功率控制的情况。
A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
在FLL时钟模块旨在满足要求的低系统成本和低功率消耗。
The FLL clock module is designed to meet the requirements of both low system cost and low power consumption.
其他的一些单片机有可能是和它相反的，在那里他们更像一个数字信号处理器，有更高的时钟频率和功率消耗。
Other microcontrollers may serve performance-critical roles, where they may need to act more like a digital signal processor(DSP), with higher clock speeds and power consumption.
时钟网路的功率消耗是晶片全部功率消耗的主要来源之ㄧ。
The shield is draining our power at an alarmingly fast rate.
时钟网路的功率消耗是晶片全部功率消耗的主要来源之ㄧ。
The shield is draining our power at an alarmingly fast rate.
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