如果在这种情况下，其解决方案也会定义出需要什么样的附加时钟分频电路。
If this is the case, the solution will also specify how much additional clock division is required.
他由一个8位6502CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
在数字系统中各个模块所需的时钟频率往往不相同，通常采用分频的方法由系统时钟得到所需频率。
Different components in a digital system often need different working frequencies, the way we often used is clock division from the system clock.
同时给出了一种提高实时控制精度的有效方法，即通过改写系统定时器的分频值达到改变定时器时钟中断频率的值。
And it presents a efficacious method to enhance precision of real time control, which changes value of clock interrupt frequency by changing divided frequency of system tinier.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
每个看门狗具有一个可选择的预分频器(从1到64K)，可用于时钟看门狗定时器也能触发dma请求和捕获比较通道。
Each watchdog has a selectable prescaler (from 1 to 64 k) that can be used to clock the watchdog timers which can also trigger DMA requests and capture compare channels.
计数器是最常用的时序电路之一，他们不只可以用来指望脉冲，还可以分频，定时，发生跳动的脉搏和其他的时钟信号等。
The counter is the most commonly used one of the sequential circuits, they not only can be used to count on pulse, still can separate frequency, timing, produce beats pulse and other clock signal etc.
端口时钟被分频为所需的频率或被保持在其原始频率。
The port clock is divided to a desired frequency or kept at its original frequency.
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
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