方法：13例眼部异物行sct扫描后分别对每一个异物作mpr和SSD处理，按时钟位定位并与手术结果对照。
Methods: After 13 cases eyes foreign bodies were scanned with SCT, each foreign body was dealed with MPR and SSD, located by clock and compared with operation.
时钟的发明者是一位名叫加扎利的工程师。
一个好的经验法则是在32位CPU上以每字节10个CPU时钟周期的速率加密。
A good rule of thumb is to encrypt on a 32-bit CPU at the rate of 10 CPU clock cycles per byte.
这个基于PowerPCe300的32位多媒体SoC采用90纳米的低功耗CMOS技术制程，时钟频率400MHz。
Fabricated with 90-nanometer low-power CMOS technology, the 32-bit PowerPC e300-based multimedia SoC is clockable up to 400MHz.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
就如一块手表或时钟显示它必然有一位聪明的设计者，同样我们奇妙的世界显明必然有一位智慧的设计师。
Just as a nice wristwatch or clock shows evidence of an intelligent designer, so our amazing world shows evidence of a brilliant designer!
大规模集成电路晶元是中等到大规模的记忆晶元，用于8位处理器、数字时钟和计算器。
Lsi chips are medium to large size memory chips, 8 bit microprocessors, digital clocks or calculators.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
本控制系统以高性能8位单片机at89c52为核心，结合数据采集电路、信号输出电路、实时时钟电路、系统监控电路组成。
The control system is composed of AT89C52, a high-powered 8-bit microcontroller, data gathering circuit, real time circuit, data output circuit and system watch circuit.
快速载波和位时钟恢复是突发模式传送系统的一个关键因素。
Rapid carrier and clock recovery is a key technique in burst mode transmission.
仿真结果表明，采用5位数控方式调谐电容阵列，调谐时间误差不超过三个时钟周期，满足系统要求。
Simulation results showed that, with 5 CNC mode tuning capacitor arrays, the tuning time error was no more than three clock cycles, which meets requirements of the system.
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
一位二十出头的匿名伦敦设计师补充说：“我的朋友圈里流传着这样一个笑料，他们说每年快到秋天的时候，我就会有一个新男朋友，好像时钟周期一样。
An anonymous twenty-something London-based designer added: 'It's a running joke with my friends that every year around autumn time I get a new boyfriend, it's like clockwork.
在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。
Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.
提出的时钟控制电路，是利用单片机at89c 2051的16位定时器做成电子时钟，并利用电子时钟的精确定时作用实现了实时控制。
This paper presents a clock control circuit in which an electronic clock is made by a MCU AT89C2051 16-bit timer and real-time control is achieved by the electronic clock's function of precise timing.
文章介绍了一种采用多时钟定量系统设计八位复杂指令集微处理器的方法。
This paper introduces the multi - clocks method in 8 - bit complex instruction set MCU system - level architecture.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
本系统利用集成时钟和数据恢复芯片SY87700L实现了可靠的位同步。
This system select integrate chip SY87700L to realize bit synchronizing reliably .
它本身不含有位同步时钟分量。
系统由AT89S52、74LS244、74LS373、八位一体数码管等部分构成，能进行时、分、秒的显示，也具有时钟校准。
System from AT89S52, 74LS244, 74LS373, eight of integrated digital and other parts, capable of hours, minutes and seconds of the show, also has clock.
他由一个8位6502CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
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