这里有点时序逻辑，今天下雨。
And here is a bit of temporal logic for you. It is raining today.
线性时序逻辑是一个已经确立的规则。
时序逻辑总是有能力原因时限。
Temporal logic always has the ability to reason about a time line.
那是因为时序逻辑，时间的逻辑就是这样运作的。
And that's because of the temporal logic that's how the logic of time works.
介绍了一种设计同步时序逻辑电路的新方法。
A new method for designing synchronous sequential circuits (SSC's) is described.
在时序逻辑，报表可以有真值，可以在不同的时间。
In a temporal logic, statements can have a truth value which can vary in time.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。
The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.
定义了稠密时间区间时序逻辑，它是区间时序逻辑的一种实时扩充。
We present a dense timed interval temporal logic and exploit the decidability problem of DTITL.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
这类系统通常用时间自动机来表示，而它们的性质则用时序逻辑公式表示。
The systems are usually described by the timed automata and the properties are specified by the temporal logic.
在时序逻辑设计中，较好地解决了数据的存储、读取和点像元数据连续监测。
Data storage, reading and continuous monitoring of point pixels have been well solved in design of time sequence logic.
文中主要讨论常用时序逻辑模型(D锁存器、D触发器和T触发器)的建立。
This article mainly discusses the building of such sequence logic models as D_latch, D_FF and T_FF.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
移位寄存器是用来寄存二进制数字信息，并能将存储的信息移位的时序逻辑电路。
The shift register is a sequential logical circuit, which can store and shift binary digit information.
CMOS敏感器不是I2C总线电路，因此同arm连接必须有驱动电路(时序逻辑电路)。
When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.
这种分析和设计方法也适用于同步时序逻辑网络，并且适用于使用计算机进行辅助分析和设计。
The methods of the analysis and design can also be used for synchronous sequential logical networks and for CAA and CAD as well.
既是一个时序逻辑系统也是一个程序设计语言，它能表示普通高级语言中几乎所有的重要机制。
XYZ/E is a temporal logic system as well as a programming language. It can represent almost every kind of significant features in conventional imperative languages.
文中，作者设计并实现了一种根据程序的线性时序逻辑(LTL)的性质产生测试预言的方法。
In this paper, we design and implement a method of producing test oracle from program's LTL (Linear Temporal Logic) property.
巴斯先生用来实现这一转化过程的工具是线性时序逻辑，一种可以表达过去和未来的详细约束的数理逻辑系统。
The tool Mr Barth is employing to effect this transition is linear temporal logic, a system of mathematical logic that can express detailed constraints on the past and the future.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。
State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
采用近世代数和时序逻辑的方法定义了形式化描述语言，并形式化地描述了密码协议的分层安全需求。
Using temporal logic and algebra, a formal requirement language was presented and used to describe the formal hierarchy requirements for cryptographic protocols.
有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
本文利用四值逻辑讨论了触发器的逻辑功能，并讨论四值逻辑在脉冲异步时序逻辑网络分析和设计中的应用。
This paper has discussed the logic behaviour of flip-flops using the four valued logic and its applications in the analysis and design of pulsed asynchronous sequential logical networks.
介绍以中规模集成计数器为核心，结合中规模集成组合逻辑器件及少量门电路进行时序逻辑电路设计的方法。
This paper introduces one way to design scheduling logic circuit with medium-scale integrated counter at the core and based on MSI.
提出采用时序逻辑系统描述故障的概念，推演故障的性质和相互关系，对故障进行分类，并预测将要发生的故障。
The temporal logic system is proposed to describe the concepts of faults, inter the attributes of faults with their correlation and classes, and predict what faults will happen.
本文的不足之处是没有对其他模块如寄存器模块和位时序逻辑模块等进行详细的研究和设计，以后还需要做进一步的工作。
The shortcoming of the article is the lack of the detailed study and design of other modules such as the register module and bit timing logic modules. Further work needs to be done later.
本文的不足之处是没有对其他模块如寄存器模块和位时序逻辑模块等进行详细的研究和设计，以后还需要做进一步的工作。
The shortcoming of the article is the lack of the detailed study and design of other modules such as the register module and bit timing logic modules. Further work needs to be done later.
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