本文提出异步时序电路的设计方法。
A method of designing asynchronous sequential circuits is presented.
提出一种基于状态转换图的时序电路等价验证算法。
A sequential equivalence checking algorithm based on state transfer graph is presented.
本文针对时序电路的初始化提出一种新的实现方法。
This paper presents a new approach to the automatic generation of initialization for synchronous sequential circuits.
解决了CCD的时序电路及功率驱动电路设计问题。
The paper designs the circuits of working clock and power driver for CCD.
文章还介绍了该双边沿触发器在时序电路中的应用。
The application of this type of double-edge-triggered flip-flop in seq…
提出了在SPICE中建立数字时序电路宏模型的新方法。
A new method of developing digital sequence circuit macro-models in SPICE is proposed in this article.
本文还针对异步时序电路测试生成问题进行了有益的研究。
In this dissertation, some beneficial researches on test pattern generation for asynchronous circuits are taken.
本文提出三值触发器串接时序电路，用实例阐述综合方法。
The sequential circuit with ternary. flip-flops in series is proposed. The synthesis for the above circuit is discussed with an example.
如何实现同步时序电路的初始化是时序电路测试中的关键问题。
How to implement the initialization for synchronous sequential circuits is a important issue.
本文提出迁移函数法。用此方法可以解决多变量时序电路综合问题。
This paper presents a transition function method which can be extended to solve the synthesis problems of multiple variable sequential circuits.
重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术。
The optimization and asynchronous design of sequencing circuits and high level circuit design and optimizing techniques are described in particular.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
它能把组合电路和时序电路的位级描述的设计规范表示成字级多项式。
It can translate the bit level description of the specification of combinational circuits and sequential circuits into word level polynomials.
对不可测故障进行测试产生是影响时序电路测试产生效率的一个重要因素。
Testing generation of un test faults is a major factor influencing the efficiency of sequential circuits testing generation.
然而，已有的电路并行测试生成算法并未取得理想的结果，尤其对时序电路。
However, the existing circuit parallel test generation algorithms fail get good results, especially for sequential circuit.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。
Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
然而，高效的产品测试技术依然是异步时序电路大规模应用的一个很大的障碍。
However, an efficient and effective production test technique is the final hurdle of the mass application of the asynchronous circuits.
及对时序电路逻辑功能的两种检测技术：基于状态表的测试技术和自动检测技术。
Two test technologies state stable based technology and automatic test technology are given for the test of logic functions of sequential circuit.
在数字电路中，数字频率计属于时序电路，它主要由具有记忆功能的触发器构成。
In the digital circuit, the digital frequency meter belongs to the sequence circuit, it mainly by has the memory function trigger constitution.
为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
通过两个典型例子，介绍了卡诺图应用于同步时序电路的逻辑分析和逻辑设计的方法。
With two concrete examples, this paper discusses the application of Karnaugh figure in synchronous time-sequence logic circuit's analysis and design.
通过设计实例表明，基于触发器次态方程设计同步时序电路具有一定的优点和实用意义。
Some design examples show that the design of synchronous sequential circuits based on next state equations of flip-flops is of great advantage and practical significance.
系统根据引信时序电路中被测对象的特点和测试需求，建立了专用测试系统的硬件平台。
A hardware platform of special test system was constructed by the characteristic and test requirement.
基于无复位时序电路，详细研究了有复位状态的同步电路测试生成问题及在无复位电路中的应用。
In order to test the circuits that has not any reset state, special way for resolving start state is described.
分析了MSI计数器74161的逻辑功能，它作为通用的时序部件可以实现任意同步时序电路。
The logic functions of MSI counter 74161 was analysed. It could be taken as a universal sequential module to realize any synchronous sequential circuits.
这不仅大大简化了时序电路的设计过程，而且能满足现代设计关于系统性、清晰性和可靠性的要求。
Therefore, it not only greatly reduces the design procedure of sequential circuits, but can also meet the need of contemporary design on its systematization, clarity and reliability.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
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