本文提出了逻辑法设计时序控制电路的改进方法。
An improvement of logic design approach for time-sequence control circuit is presented.
PLC编程技术包括：经验设计法，逻辑设计法、时序图设计法、顺序控制设计法等编程方法。
PLC programming technique includes experience design method, logic design method, cycle diagram design method and sequential control design method.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。
State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
HL 2A控制系统由时序控制系统，逻辑控制系统和反馈控制系统三个部分组成。
The HL-2A control system consists of timing system, PLC logic control system and feedback control system.
此装置可以根据逻辑时序图直接对逻辑控制模块进行编程和参数设置。
The unit can directly program the logical control module and set parameters based on logical time sequence.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
给出了具有实际应用价值的APD信号放大电路和控制时序逻辑电路原理图。
The article offers APD signal amplify circuit chart and controlling time series logic circuit principle chart bearing practical applied...
该控制器是由多种逻辑集成器件构成的典型时序控制电路。
This controller is the typical sequential control circuit which is constituted by many kinds of logical integration component.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该方案将被叠加的字符或图像数据保存在FPGA内部的ROM中，由内部逻辑控制电路产生点阵时序，控制视频通道切换开关，完成叠加功能。
The data of overlapped characters and pictures are stored in the ROM of FPGA, The Times are generated by FPGA inner logic circuit to control the switch of TV channels to finish the overlapping work.
给出了具有实际应用价值的APD信号放大电路和控制时序逻辑电路原理图。
The article offers APD signal amplify circuit chart and controlling time series logic circuit principle chart bearing practical applied value, which possess some guidance significance...
基于FPGA (EP1K100 QC 208)的16位定点复数的快速求模设计及系统时序和控制逻辑设计。
Design the fast calculation of modulus of 16 bit fix-point complex number and time logic of pulse compression system based on FPGA (EP1K100QC208).
系统以ARM微处理器和FIFO存储器为核心，利用可编程逻辑器件实现对整个底层数据采集系统的逻辑控制，并给出了时序控制部分的仿真波形。
The system controls the logic of the data acquisition board by programmable logic device (PLD) with the center of the ARM microcontroller and FIFO memory and provides the simulate waveforms.
CIP工艺流程及其智能型的控制点流程、时序要求以及应用可编程序控制器（PC）来实现CIP的逻辑控制。
Technological process of CIP and intelligent CIP technological process of control point. Require of time sequence and appliance of PC to realize logical control of CIP.
利用延迟，使控制逻辑符合时序的要求。
With the help of delay time, control logic accomplish the demand of sequential circuitry.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
逻辑控制电路由CPLD完成，主要完成整个处理单元的时序和逻辑控制。
Logical control circuit is implemented by CPLD, and its main function is the whole units time sequence and logical control.
对于系统中复杂且高速的逻辑控制及时序设计及其实现的阐述是论文的另一重要部分。
Also, this paper details the complex and high-speed logic control and timing schedule design.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
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