用一片CPLD芯片就完成了全部的译码、时序控制、显示控制等功能，这样CPU和LCD之间就可能直接用一个CPLD芯片连接了，无需再加入其它的接口器件。
Realizing all needed function such as encoding, sequence control, display control and so on with only one CPLD chip, it can be used to connect CPU with LCD without any other devices.
自启动预载接口芯片以控制为主，时钟关系复杂。时序设计是整个设计的重点和难点。
Interface and download chip is control-oriented and has complex clock relationships, therefore timing design is the key and difficult point.
并着重研究了系统的硬件设计，讨论了CPLD的时序控制、图像传感器的寄存器控制以及DSP芯片的硬件开发、软件实现、实验分析等等。
We put emphasis upon systemic hardware design, discuss the sequence control of CPLD, Register control of image sensor, and hardware exploiture, software realization, empirical analysis of DSPs, etc.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
利用单片机IO口模拟I2C时序，实现了视频解码芯片控制；
To system needs, video decode program is designed by simulation of MCU's IO to I2C time sequence.
利用单片机IO口模拟I2C时序，实现了视频解码芯片控制；
To system needs, video decode program is designed by simulation of MCU's IO to I2C time sequence.
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