本页解释ICMP时间戮记如何使用来解决时序同步化议题。
This page explains how ICMP timestamps are used to solve clock synchronization issues.
这种异步与门与常用的同步型爆炸与门相比，具有对两个输入信号无同步性和无时序要求的特点，扩展了与门的应用范围，提高了正常作用的可靠性。
Compared with synchronous explosive and gate, it requires no synchrony and time sequencing to its two inputs, thus extends its application area and improves its reliability of normal function.
这种分析和设计方法也适用于同步时序逻辑网络，并且适用于使用计算机进行辅助分析和设计。
The methods of the analysis and design can also be used for synchronous sequential logical networks and for CAA and CAD as well.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
在时序方面采用CPLD来控制，同时实现了频率的跟踪和同步采样功能。
In the time sequence control respect, it USES CPLD to realize frequent tracking and synchronized sampling function.
选择时钟方案是同步时序集成电路设计的前提。
Selecting one clock scheme is the basis of designing synchronous systems .
通过设计实例表明，基于触发器次态方程设计同步时序电路具有一定的优点和实用意义。
Some design examples show that the design of synchronous sequential circuits based on next state equations of flip-flops is of great advantage and practical significance.
通过两个典型例子，介绍了卡诺图应用于同步时序电路的逻辑分析和逻辑设计的方法。
With two concrete examples, this paper discusses the application of Karnaugh figure in synchronous time-sequence logic circuit's analysis and design.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
同步时序机的状态驱动可根据状态图来完成，状态图通常由次态方程求得。
The state drive of a synchronous sequential machine may be finished according to the state diagram which is usually derived from the next state equation.
基于无复位时序电路，详细研究了有复位状态的同步电路测试生成问题及在无复位电路中的应用。
In order to test the circuits that has not any reset state, special way for resolving start state is described.
从工程应用的角度出发，同步时序电路故障模拟采用单测试码故障并行的模拟结果更能反映实际情况。
Presented and implemented in this paper is a fanout source based fault parallelism fault simulator for synchronous sequential circuits.
对异步时序电路的分析和使用是一个比较困难的问题，所以，异步时序电路的实际应用范围远不如同步时序电路。
It is rather difficult to analyze and make use of asynchronous sequential circuits, so the application of asynchronous sequential circuits is much narrower than synchronous ones.
这为进一步将该算法拓展至实际的多输出组合网络乃至同步时序网络打下了基础。
This makes it possible for the extension of our algorithm to multiple-output combinational network and even sequential network.
下图是一个通常的同步读周期的时序图。
Figure below provides the timing diagram of a generic synchronous read cycle.
本文在同步时序电路故障模拟器—HOPE的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。
Base on the existing synchronous sequential circuits fault simulator-HOPE, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly.
分析了MSI计数器74161的逻辑功能，它作为通用的时序部件可以实现任意同步时序电路。
The logic functions of MSI counter 74161 was analysed. It could be taken as a universal sequential module to realize any synchronous sequential circuits.
提出同步时序设计的“心跳法则”，总结了以软描硬的调试理论。
The heart rule of synchronization timing design was proposed. The debugging theory of software for hardware was summarized.
同步时序机状态加全模拟是同步时序机反设计的关键步骤。
Full state simulation is a key step in the reverse DE - sign of synchronization sequential machine.
介绍了一种设计同步时序逻辑电路的新方法。
A new method for designing synchronous sequential circuits (SSC's) is described.
如何实现同步时序电路的初始化是时序电路测试中的关键问题。
How to implement the initialization for synchronous sequential circuits is a important issue.
支持长短按键的键盘驱动与普通的键盘驱动在时间要求上有所不同，对时序进行分析后，利用同步机制设计与实现了键盘管理模块。
Because the press-and-hold keyboard driver is different from the normal driver, it is very important to analyze temporal coherence before driving the keyboard.
同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。
The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price; but due to its complex control timing, it cannot directly interface with DSP.
介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案——一个有效的符号模型判别器veris。
A solution for property verification of synchronous VHDL design is introduced, and VERIS an efficient symbolic model checker is implemented.
跳时序列的数目即是该通信系统中用户的数目，同时它也是整个通信系统同步与信道检测的技术上的保证。
The number of time-hopping sequences directly determines the number of users in the communication system, while it is also a reliable guarantee of the synchronization and channel detection.
数据的跨时钟域传输对于长期仅接触同步时序设计的设计者而言是一个巨大的挑战。
It is a great challenge to a designer who is only familiar with the single clock-domain design.
提出了一种改进时序重排算法，使时序重排可以更有效地与其他组合优化算法结合起来，共同提高同步时序电路的速度。
This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.
设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。
Design of synchronous cycle trig based on internal bus, consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance.
设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。
Design of synchronous cycle trig based on internal bus, consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance.
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