正如文中所指出的那样，绝大多数组合与时序优化问题，实际上都是NP -完全问题，因而试图给出现实可行的一劳永逸的通用算法在目前是办不到的。
Just as this paper points out, most problems about combination and sequential optimization are in fact NP-complete, so, it's impossible to find a general algorithm to solve all the problem presently.
研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。
The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
本文最关键的工作在于图像采集的时序控制和匹配算法的优化实现。
The most decisive works lie in the control of the image-capturing timing and the optimization of the image-matching arithmetic.
重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术。
The optimization and asynchronous design of sequencing circuits and high level circuit design and optimizing techniques are described in particular.
有效重定时的判定算法是重定时优化的关键，因此也是时序调整策略的关键。
The effectivelyretiming determining algorithm is key of retiming, so it is the key of sequence adjust strategy.
提出一种具有逻辑时序特征的微粒群优化算法，并将其应用于半导体封装生产线的工序参数优化中。
A kind of particle swarm optimization method with the characteristic of logical time-sequenced is proposed and applied to procedure parameters optimization of semiconductor assembly product line.
对照数据手册的时序要求优化硬件逻辑设计，解决了双核嵌入式处理器TMS320 VC 5471和USB芯片PDIUSBD12时序不兼容的问题。
We have optimized the hardware logic according to the timing requirement on datasheet, and solved the timing incompatibility between the dual-core processor TMS320VC5471 and the USB chip PDIUSBD12.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
提出了一种改进时序重排算法，使时序重排可以更有效地与其他组合优化算法结合起来，共同提高同步时序电路的速度。
This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.
时钟频率的提高，时序收敛性问题则变的越来越重要，时序的优化则成为设计的主要目标。
Higher work frequency makes timing convergence more and more important, timing optimization becomes the main objective of the design.
对MCNC标准单元测试电路中组合和时序电路的实验结果显示， 电路经过时延驱动优化布局后的最大路径时延最多减少了31%。
MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.
逻辑优化可以跨越层次结构：采用该设置可以令逻辑优化在全局跨越式进行，从而获取更好的时序性能。
When this property is set to True (checkbox is checked), Map ignores any Keep Hierarchy properties set for the Synthesize process and Map can perform. optimizations across any hierarchical boundaries.
逻辑优化可以跨越层次结构：采用该设置可以令逻辑优化在全局跨越式进行，从而获取更好的时序性能。
When this property is set to True (checkbox is checked), Map ignores any Keep Hierarchy properties set for the Synthesize process and Map can perform. optimizations across any hierarchical boundaries.
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