数据电路暨数字调制解调器(dsu)由本公司供租与维护。用户终端设备(CPE)由用户自备与维护。
Data Circuit and Data Service Unit (DSU) are provided and maintained by CHT while the customer Premises Equipment (CPE) is provided and maintained by the customer.
实时时钟电路（X1228）被用作里程表，数据存储器和车速表中的警报。
A real-time clock circuit(X1228)is applied to be an hourmeter, data memorizer and alarm in speedometer.
问题是，用来制造逻辑电路的晶体管中保留着它们的电子态，因此当这些晶体管通电的时候，它们会包含任何可能的数据。
The problem is that the transistors used to make logic circuits hold their electronic state, and therefore any data they contain, only when powered up.
某些传感器自身就具有数据平滑内部电路。
Some sensors have their own data smoothing internal circuitry.
今天，它采取的形式是集成电路，使存储的数据进行访问的任何命令(即随机)。
Today it takes the form of integrated circuits that allow the stored data to be accessed in any order (ie, at random).
由于提供了数字输出，数字传感器不需要外部电路进行线性化和数据转换。
By providing a digital output, digital sensors do not require external circuitry for linearization and data conversion.
通过对数据接收电路CPLD内部参数的调整，可以实现对各种数字接口器件的配置，从而使得电路控制更加简单、灵活与可靠。
By adjusting parameters in CPLD of data receiving circuits, we can implement configuration of all kinds of digital interface devices, which makes the circuit control simpler, neater and more reliable.
设计了一个串口通讯的单片机数据采集模块，文中详细阐述了模块的电路原理和程序设计。
Design a data collection module with serial port based on microcontroller. The thesis explains the circuit principle and program designing in detail.
分析了电路波形及实验数据、对实验研究过程中的多频率峰值、谐波干扰和幅值干扰等进行了分析和处理。
A detailed analysis about the circuit waveform and experimental data is also given the multi-frequency peak value and the frequency interference during the experiment are all analysed and processed.
用一组实测数据验证电路设计的合理性。
The rationality of the circuit design is validated by a group of practical test data.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
两个单稳态电路提供数据和滤波信号。
A twin monostable circuIt 'supplies the data and strobe signals.
在舵机控制电路参数的测试过程中，选择适当的数据处理方法与优化测试电路性能，对于提高测试精度是同等重要的。
In the testing system, it is same important to select an appropriate data processing method as to optimize performance of hardware to improve the test accuracy.
本文阐述了系统的结构和工作原理，搭建了直流毫伏表的硬件电路，并设计了软件系统中的数据采集处理和显示部分的程序。
This paper describes the system structure and working principle, to build a DC mV meter hardware and software system design of data acquisition and processing and display part of the process.
硬件部分主要包括应变电阻片、信号检测电路、数据采集与处理系统等。
The part of the hardware includes strain resistance, signal detecting circuit, data acquisition and processing system, etc.
本文介绍一种用于空间及核数据采集系统中的高速数据交换电路它具有低功耗、高速度的特点。
This paper describes a circuit of data exchange with the features of high speed and low power dissipation.
通过软件设计和硬件电路的结合，实现了数据采集电路的模块化设计，提高了系统的精度和可靠性。
By combining software design and hardware circuit, the modularization of designing data acquisition circuits is fulfilled, and the accuracy and reliability of the system are enhanced.
介绍了一种数据采集硬件电路的柔性设计方法。
This paper proposed a flexibility design of a data acquisition circuit.
研制了一种用于X射线探测的阵列探测器SSPA器件，进而研究了适用于该器件的数据采集电路。
After SSPA used as X-ray array detector is developed, we take a research on the data acquisition circuit applied to the detector.
使用FPGA设计了数据采集电路，降低了成本，提高了可靠性，系统具有升级容易、开发周期短等优点。
We use FPGA to design data collection circuits, so the costs are reduced, reliability is improved and the system is easy to upgraded and developed.
转换器的分辨率决定着数据采集电路的量化精度。
The quantization precision of data acquisition circuit is determined by the A/D's resolution.
给出了系统总体结构、模拟通道设计、倍频锁相电路、数据采集电路、各种电参数测量算法及系统软硬件抗干扰措施。
The system hardware structure, analog channels circuits, data acquisition circuits, measurement algorithms of electric parameters and anti-jamming methods are given.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
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