本文采用逻辑电路实现了基于采样数据的EPLL数字锁相环算法，并在FPGA电路中实现和实验验证该设计。
Through the adoption of the logic circuits, this article will successfully actualize the EPLL, which is based on the sample data, and validate this project in FPGA.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
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