在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
从声波干涉的基本原理出发，通过数字延时线的简化分析，说明了多级台阶反射声的叠加对声波频率产生的梳状滤波效果。
Based on principals of interference of acoustic waves and simplified digital delay-line, comb filter effect induced by superposition of reflections from steps is presented.
文中提出了一种基于数字式FFT接收机体制下的延时引导的解跳方法。
Based on the system of digital FFTreceiver, a "Time delay guiding" de-hopping method is introduced.
本论文就是针对这种情况，实现了一种多功能的数字音频实时延时处理器，并编制了相应的应用软件。
Under such condition, we will introduce a versatile real time delay processor for digital audio signal (RTDP) and its application which has been made by myself in this paper.
数字控制器存在采样与计算延时，实时控制性差，采用数字控制器实现双闭环瞬时值控制比较困难。
But it is hard to realize the dual-loop instantaneous control with digital scheme, because there is delay time of sampling and computing and lack of real-time regulation for digital control.
按钮式控制数字电位器x 9511由延时去抖动电路、单稳电路、触发器组成。
Button control digital potentiometer X9511 is consists of time delay circuit removed dithering, mono - stability circuit, preventative dithering trigger.
该系统采用了直接数字频率合成技术(DDS)和并发处理技术，提高了系统的性能和处理速度，较大程度地减少了硬件延时。
The system USES direct digital synthesize (DDS) and parallel processing technique, improves the performance and speed of the processing, and reduces the hardware delay mostly.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
提出了有源钳位准谐振变换器的一种新的驱动方式，它无需经过数字电路延时，只需一个电阻和二极管构成的小网络。
This paper proposes a new gate drive method for active clamped quasi resonant converters. Instead of a digital delay circuit, only a resistor and a diode are added to produce correct drive waveforms.
为了有效地抑制网络延时对网络控制系统性能的影响，提出了一种鲁棒数字比例积分微分(PID)控制器设计方法。
In order to restrict the influence of network-induced delays on the performance of networked control systems, a novel robust proportional-integral-differential (PID) control technique was proposed.
采用高并行度的并行延时最小均方(PDLMS)算法，用现场可编程门阵列(FPGA)实现自适应数字波束形成模块。
A new digital beam forming (DBF) method is proposed. It combines the parallel delay LMS (PDLMS) algorithm and the field programmable gate array (FPGA).
利用FPGA作为数字信号处理平台来实现可调的衰落带宽以及多径延时。
The adjustable fading bandwidths and additional long delays were implemented by using the relative new signal processing technologies of FPGA device.
介绍了一种采用CMOS数字电路、数字拨盘开关整定、无辅助电源的断电延时继电器的组成及工作原理。
Introduction was made to the composition and working principle of a power-off time delay relay which adopts CMOS digital circuit, digital dial disc for switch setting and without auxiliary power.
这些报警功能的数字设定点控制，延时定时器，和普遍的投入。
These alarms feature digital setpoint controls, delay timers, and universal inputs.
采用模拟回波和精密延时电路检测照射能力、用CCD采集激光光斑测试激光束散角，实现了整机性能的数字化检测。
Using simulation echo wave and accurate time delay circuit to measure ranging ability, using CCD to grasp laser facular to measure divergence of laser pulse, the digitized methods are realized.
PSK非相干解调法将经延时半个载波周期的接收信号与原接收信号相加，检测出两相邻码元载波相位变化情况，从而解调出数字信息。
Non coherent demodulation for 2PSK detects relation of carrier wave phase of the interval symbol by the (half period of carrier wave) delay and the adder, then the data is demodulated.
从采样，计算延时，控制对象的零阶保持离散化等方面分析了数字化过程对有源电力滤波器性能的影响。
From sampling, calculation time delay, control object zero-order discretization, digitalization process influence to Active Power Filter is analyzed in this paper.
从采样，计算延时，控制对象的零阶保持离散化等方面分析了数字化过程对有源电力滤波器性能的影响。
From sampling, calculation time delay, control object zero-order discretization, digitalization process influence to Active Power Filter is analyzed in this paper.
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