本文定位于在信息截获背景下的数字分接阶段的实时码速恢复问题的研究。

This paper focuses on the research of real time justification recovery in the digital demultiplexing stage under the background of information intercepting.

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本文提出了基于FPGA技术实现数字复接系统的设计方案，并介绍了基群与二次群之间的复接与分接的系统总体设计。

This paper puts forward a design method of digital multiplex system with FPGA, and introduces the whole system of multiplexing and demultiplexing between primary group and secondary group.

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在复分接系统中，如同步数字系列(SDH)，定时处理占有重要地位。

In multiplex and demultiplex systems such as Synchronous Digital Hierarchy (SDH), timing processing is very important to system performance.

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在复分接系统中，如同步数字系列(SDH)，定时处理占有重要地位。

In multiplex and demultiplex systems such as Synchronous Digital Hierarchy (SDH), timing processing is very important to system performance.

youdao