存储器则是由10个硬盘驱动器(每个硬盘容量为698GB； 7,200转数)组成，由一个硬盘控制器组织成一个逻辑卷(RAID5)。
The storage consisted of 10 hard drives (698 GB each; 7,200 RPM), organized as a single logical volume (RAID 5) using a hardware controller.
第二个JSP(清单7)将通过提供一个输入框向存储器添加一条新的消息，并通过PortletAction方法将输入的值提交回控制器以进行处理。
The second JSP (Listing 7) handles adding a new message to the store by providing an input box, and Posting the value back to the controller through a PortletAction for processing.
用于控制快闪存储器装置的命令数据输入到控制器218。
Command data for controlling the flash memory device is input to the controller 218.
执行过程中的一个阶段所需的时间，在此期间，计算机从主存储器中取出指令或操作数，并将其存入控制器或运算器的寄存器中。
The part of execution in which an operand or instruction is read from main storage and written into a control unit or arithmetic unit register.
单片机是将运算器、存储器、定时器、模数转换器和串行通信接口等集成在一个芯片上的小型计算机系统，它可以被嵌入到各种自动控制器和智能电子产品中。
Microcontroller is a small computer system that integrates ALU, memory, timer, ADC, UART, etc in one chip. it can be embedded into many kinds of controllers and intelligent electronic products.
芯片组33可以包括存储器控制器集线器(MCH)34。
对于这个方法有一些优势：我们将批处理动作的意图存储在了事件存储器中。流程控制器自动进行回滚或类似的操作。
There are some advantages to this approach: we store the intent of the bulk action in the event store. The saga automates rollback or equivalent.
控制器218通常含有缓冲存储器以用于将用户数据写入到存储器阵列或从存储器阵列读取用户数据。
Controller 218 typically contains buffer memory for the user data being written to, or read from, the memory array.
趋势是将系统的存储器阵列和控制器电路一起集成在一个或一个以上集成电路芯片上。
The trend is to integrate the memory arrays and controller circuits of a system together on one or more integrated circuit chips.
BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。
The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.
硬件部分重点论述了S3C 2410处理器与存储器和网络控制器芯片的接口设计问题。
In hardware design part, explains especially the interface of S3C2410 CPU chip with memory and network controller chip.
分析了ADC转换器单端模式下对电压信号的采集过程和DMA控制器对外部存储器写入数据的过程。
The process of data acquisition with ADC controller in single-ended mode and the process of data storage with DMA controller are described.
因此，控制器(或控制能力)可内嵌在主机中或包含在可移除存储器系统内。
Thus, the controller (or control capability) can be embedded in the host or included within a removable memory system.
此系统主要由单片机，USB主机控制器，高速RAM,FLASH存储器等器件组成，使得数码摄像头在嵌入式领域应用成为现实。
This system, which facilitates the utility of PC cameras in embedded application, is composed of MCU, USB Host Controller, high-speed RAM and FLASH memory.
研究了断路器智能控制器的非易失性存储器的设计方法。
The design method of nonvolatile memory based on intelligent controller of circuit breaker was researched.
参数表模块主要实现SDRAM存储器的控制器接口，用于图像处理时读取参数信息。
Parameter table module is the SDRAM memory controller interface for reading parameter information when image processing.
DMA控制器可以无需CPU介入而在内部存储器、外部存储器和芯片外设之间传送数据，其在DSP系统中有广泛的应用价值。
The DMA controller can transmit data among the interior memorizer, exterior memorizer and chip peripheral without the CPU intervention. It has comprehensive application value in the DSP system.
计算机包括五个基本部分：输入设备、存储器、算术逻辑运算器、控制器和输出设备。
The computers contains 5 basic sections:input , memory, arithmetic and logic, control, and output.
在这个实施例中，系统存储控制器402集成到中央处理器400上，以便提供通过互连406对系统存储器404的访问。
In this embodiment, system memory controller 402 is integrated on the central processor 400 to provide access to system memory 404 through interconnect 406.
在一个实施例中，图形本地存储控制器也集成到芯片组408上，以便提供通过互连418对图形本地存储器416的访问。
In one embodiment, graphics local memory controller is also integrated on chipset 408 to provide access to graphics local memory 416 through interconnect 418.
所述存储器控制器耦接一动态随机存取存储器。
The memory controller is coupled with a dynamic random access memory.
在区域火灾报警控制器中，FM 31256芯片的非易失性数据存储器、实时时钟、看门狗等功能，增强系统可靠性。
The nonvolatile data memory, real-time clock, and watchdog functions of FM31256 chip were adopted by region fire alarm and control device to improve the system reliability.
于一实施例中，该存储器模组包括一闪存及一控制器。
In one embodiment, the memory module comprises a flash memory and a controller.
ECC控制器将数据发送给用于将数 据传送到主机装置的直接存储器存取（DMA）缓冲器以及用于对数据进行错误 检测和纠错的ECC块。
The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data.
本发明公开了一种动态随机访问存储器（DRAM）的控制器及用户指令处理方法。
The invention discloses a controller of a dynamic random-access memory (DRAM) and a user instruction treatment method.
在接下来的时间从主存储器中取出指令和解释的处理器的指令控制器。
The time during which the next instruction is fetched from main memory and interpreted by the processor's instruction control unit.
在一个实施例中，集成到芯片组102上的系统存储控制器106对中央处理器100提供通过互连110对系统存储器子系统108的访问。
System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
处理器5和10可各自包括允许与存储器15和20通信的存储器控制器集线器(MCH) 15和20。
The processors 5, 10 May each include a local memory controller hub (MCH) 15, 20 to allow communication with memories 15, 20.
该方法还包括通过共用控制信号发出指令到选定的非易失性存储器控制器和易失性存储器中的一个。
The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the Shared control signals.
应用推荐