讨论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform.
指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。
Instruction scheduling is used to exploit the instruction level parallelism (ILP) inherent in program through reordering its instructions.
本课程的另外一个重点是运用在高性能处理器中的指令级并行的技术。
Another focus is on technologies to exploit instruction level parallelism in high-performance processors.
指令调度是在保证语义正确的前提下，改变指令执行的顺序，以提高指令级并行的程度。
To change the execution order of instructions, enchant ILP furthest, will achieve higher performance on the basis of ensuring correctness.
谓词执行技术能够将多个基本块合并为一个超块，扩大指令调度范围，开发更多的指令级并行。
Several basic blocks could be merged into a hyperblock in predicated execution so that instructions could be scheduled on a larger scope and more instruction level parallelism could be extracted.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
谓词支持是IA 6 4体系结构的新特征，它为发掘指令级并行提供了更多的机会，同时给编译器的设计者增加了难度。
Predication support is one of the new features of IA-64, which offers more opportunities for exploiting instruction level parallelism, however, brings some difficulties for compiler designers.
通过分析影响嵌入式系统性能的主要因素，采用了基于线程概念的嵌入式系统并行设计方法，利用指令级并行来改善系统性能。
By analyzing factors impacting upon the embedded system performance, an embedded system design method based on thread ideas is used, performance is improved with instruction level parallelism.
最后，通过ILP对该策略提出改进，以指令级并行信息指导功耗优化，在功耗优化效果损失不大的前提下，可节省多达20%的算法开销。
At last, an enhancement method for the strategy is proposed based on ILP information. The statistics shows that the cost saved can reach up to 20%.
最后，通过ILP对该策略提出改进，以指令级并行信息指导功耗优化，在功耗优化效果损失不大的前提下，可节省多达20%的算法开销。
At last, an enhancement method for the strategy is proposed based on ILP information. The statistics shows that the cost saved can reach up to 20%.
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