目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
There are some common methods of design for testability, such as boundary scan test and so on.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
提出了一种在内建自测试(BIST)中进行部分扫描的算法,此算法综合了电路的结构分析和可测性分析。
A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法,它在工业界得到了广泛的应用。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
本文在对目前主要的可测性设计方法进行研究的基础上,根据所设计CPU的结构特点,采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
扫描技术和边界扫描技术是目前可测试性设计的主流技术,可分别用来解决芯片内部与芯片之间的可测试性问题。
Scan technique and boundary scan technique are the main stream technology of current DFT technique. They can solve the internal testable problems and the connection problems between ICs respectively.
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法,弥补了传统测试的缺陷,为复杂的电路互连提供了测试手段。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
全扫描设计通过提升电路的可控制性和可观察性,大大降低了测试生成的复杂度,被认为是最有效的可测性设计方法之一。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
全扫描设计通过提升电路的可控制性和可观察性,大大降低了测试生成的复杂度,被认为是最有效的可测性设计方法之一。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
应用推荐