这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
一旦你开始调整GTL ref电压(单独针对每个核心数据和地址总线)你将会发现不同的总线频率需要不同的电压组合。
Once you begin adjusting GTLREF voltages (for each core data and address bus) you will find that different bus frequencies respond differently to variations in the voltage.
强大，灵活的5立体声总线，24位数字的影响引擎提供了广泛的时间，频率和动态的影响以及影响链接。
Powerful, flexible 5-stereo bus, 24-bit digital effects engine offering a wide range of time, frequency and dynamic based effects as well as effects chaining.
一旦选择了时钟源，可以有多种控制最终总线频率的选择。
Once you select the timing source, you have many options for controlling the final bus frequency.
本设计主要包括两个部分：基于FPGA的频率、相位检测模块和CAN总线通信模块。
So, this thesis includes two main parts: frequency and phase detecting module base on FPGA, and CAN-bus communication module.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。
The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
据我们观察所得，只有提高频率的国旗模型，并使之多样化的，其余加速器由频率的工作，系统总线进入内存和其数量。
We observe only raising the frequencies of flag models and diversifying the remaining accelerators by the frequencies of work, the system bus of access to the memory and its volume.
随着总线频率以及总线负荷的增加，基于总线的系统可靠性问题就必须引起重视。
Increasing bus frequencies and the load on the bus calls for focus on reliability issues in bus based systems.
随着总线频率以及总线负荷的增加，基于总线的系统可靠性问题就必须引起重视。
Increasing bus frequencies and the load on the bus calls for focus on reliability issues in bus based systems.
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