微处理器的一般结构：寄存器组，寄存器管理，总线时序，工作模式以及类型提供配置。
The general composition of microprocessor: register group, register management, bus line sequential, working mode and type offer configuration.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用STD总线和模块式结构，以时序鉴别法选线技术，准确定位故障线路，并发出语音报警、灯光及数字显示。
The paper adopts STD bus and modular structure and uses sequence identification wire selection technique to correctly locate the fault lines and indicate with language alarm, light and digitals.
给出了PCI总线配置空间的设计以及PCI接口控制器中时序状态机的实现。
The design of the PCI bus in the interspaced ordonnance, and the realization of the sequence state machine in the PCI interface controller is given.
CMOS敏感器不是I2C总线电路，因此同arm连接必须有驱动电路(时序逻辑电路)。
When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
给出了PC并行口与常用I2C器件AT24C02的接口方法实例，介绍了用PC并行口模拟I2C总线控制时序的实现方法。
To provide examples about the interface of common I2C and AT24C02. And then to introduce the methods of simulating controlled I2C Bus interface with PC parallel socket.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。
Design of synchronous cycle trig based on internal bus, consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
最后，在研究EP -H31580 1553总线芯片的基本功能和读写时序的基础上，完成了1553总线模块的硬件设计。
At last, 1553 bus circuit design has been finished on the basis of studying the basic function and timing of 1553 chip EP-H31580.
给出了一种基于FPGA实现PCI总线目标模块接口控制器的设计方案，用时序状态机来实现总线访问操作复杂的时序。
PCI target interface controller design with FPGA is proposed. And the realization of the complication of the access sequence to the BUS interface controller is expressed by sequence state machine.
正确使用单总线数字温度传感器，分析其时序关系，基于时序编制正确程序具有及其重要意义。
Using the single bus temperature correctly, analyzing time slots and designing the program based on correct time slots have an important meaning.
它是一个单总线温度传感器，需要严格按照时序工作。
It is a single main line temperature sensor, needs strictly according to the succession work.
它是一个单总线温度传感器，需要严格按照时序工作。
It is a single main line temperature sensor, needs strictly according to the succession work.
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