八路三态反相总线收发器。高性能硅栅cmos。
Octal 3-state inverting bus transceiver. High-performance silicon-gate CMOS.
八路三态同相总线收发器。高性能硅栅cmos。
Octal 3-state noninverting bus transceiver. High-performance silicon-gate CMOS.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
CAN总线接口采用协议控制芯片SJA1000，配以收发器82c250。以太网接口采用以太网控制器rtl 8019as作为物理层传输媒介。
CAN-BUS interface adopts protocol control chip SJA1000 plus receiving and sending chip 82c250. Ethernet interface adopts Ethernet controller RTL8019AS as physical transmission media.
接下来对本系统所用到的CAN总线的原理、CAN控制器和CAN高速收发器进行了详细的介绍，并给出了CAN总线接口的设计方案。
Then detailed representations for CAN-BUS principle, CAN controller, CAN high-speed transceiver, and design project for CAN-BUS interface were given.
两级系统通过收发器同CAN总线连接并实现数据的互换。
The two levels of the design is connected by CAN Bus through the transceiver (TJA1050).
在数据通信方面，提出了由总线控制器与报文收发器构成的CAN总线接口电路，并详细论述了与总线接口初始化、总线中断处理、总线数据收发相关的设计实现过程。
For the purpose of data communication, the paper lodges the CAN interface circuit, and expatiates the programs of bus initialization, bus interrupt service routing, receiving and sending bus data.
在数据通信方面，提出了由总线控制器与报文收发器构成的CAN总线接口电路，并详细论述了与总线接口初始化、总线中断处理、总线数据收发相关的设计实现过程。
For the purpose of data communication, the paper lodges the CAN interface circuit, and expatiates the programs of bus initialization, bus interrupt service routing, receiving and sending bus data.
应用推荐