访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
该方法将PCI总线接口和控制逻辑集成于一片FPGA中，提高了系统的集成度和可移植性。
The method which integrates PCI bus interface and control logic into a FPGA chip improves the integration density and transplantation of system.
介绍了CAN总线适配卡的接口电路和译码逻辑。
In this paper, the hardware interface and decode logic of CAN adapter are introduced.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
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