访问内部统一二级处理器缓存的后端总线接口逻辑。

Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.

youdao

访问内部统一二级处理器缓存的后端总线接口逻辑。

Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.

youdao