给出了PCI总线配置空间的设计以及PCI接口控制器中时序状态机的实现。
The design of the PCI bus in the interspaced ordonnance, and the realization of the sequence state machine in the PCI interface controller is given.
给出了PC并行口与常用I2C器件AT24C02的接口方法实例，介绍了用PC并行口模拟I2C总线控制时序的实现方法。
To provide examples about the interface of common I2C and AT24C02. And then to introduce the methods of simulating controlled I2C Bus interface with PC parallel socket.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
给出了一种基于FPGA实现PCI总线目标模块接口控制器的设计方案，用时序状态机来实现总线访问操作复杂的时序。
PCI target interface controller design with FPGA is proposed. And the realization of the complication of the access sequence to the BUS interface controller is expressed by sequence state machine.
给出了一种基于FPGA实现PCI总线目标模块接口控制器的设计方案，用时序状态机来实现总线访问操作复杂的时序。
PCI target interface controller design with FPGA is proposed. And the realization of the complication of the access sequence to the BUS interface controller is expressed by sequence state machine.
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