本文介绍了一种总线仲裁器的逻辑电路。
In this article the design of a cost-effective bus arbiter is discussed.
总线仲裁器模块广泛地应用于控制类芯片的各个领域。
Bus arbiter module is used in many fields of industry control.
通过系统各次操作的优先级关系和总线仲裁阈值的策略来防止总线冲突。
Then the priority of operation and bus arbitration threshold strategies are studied to prevent bus conflict.
另外，提出了性能比较好的本地总线仲裁算法，为后续开发做了理论上的探索。
In addition, a new algorithm for local bus arbitration is put forward, which is helpful in theory for future development.
文章介绍了在PCI系统结构中新的总线仲裁机制，提出了加权优先循环算法。
This paper presents a new PCI arbitrating scheduling scheme to support premium service in the PCI system architecture, called Weighted Priority Rotational Algorithm.
动静态混合算法不仅在总线仲裁器模块设计中具有指导意义，而且在其它控制类芯片中也具有很好的参考价值。
This algorithm is of reference value in the design of industry bus arbiter chip, so does in other systems.
它为多总线主设备系统以及远程方式下的8089IOP提供总线仲裁，它还具有双极型的缓冲与驱动能力。
The 8289 provides system bus arbitration for systems with multiple bus masters, Such a, an 8086 CPU with 8089 IOP in its REMOTE mode, while providing bipolar buffering and drive capability.
描述了CMMS系统结构及总线仲裁链式环逻辑，介绍了通信软件设计思想，并给出了发送和接收程序流程图。
The architecture and logic of chained arbitration-bus, the design idea of communication software, and the diagrams about transmitting and receiving are given.
本系统充分利用CAN无破坏性的基于优先权的总线仲裁机制，解决了多个教室同时操作时引起的总线冲突问题。
This system makes best use of CAN's non-ruinous characteristics that are based on priority of bus arbitrage mechanism, solving the bus conflict issue of multi-classroom simultaneity operation.
总线仲裁器用于对嵌入式的总线进行仲裁，文中完成了一个循环优先级仲裁器的设计，它可以保证各功能单元对总线访问的机会均等。
Bus arbiter was used to arbitrate the embedded bus. A round-robin arbiter was completed in this paper, it can ensure every unit has the equal opportunity to access the on-chip bus.
PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。
PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM.
本接口采用存储器访问模式，克服了某些CPU外围通信接口少的缺点，易于实现双CPU间的总线对接，且无需考虑复杂的总线仲裁机制。
This type of bus interface can be accessed by memory mode and be applied to the exchange of data between two hosts, which can overcome the lack of communication interface in some types of CPU.
实现PCI9054与计算机PCI总线的接口，包括总线仲裁，寄存器读写操作，EEPROM的配置和下载，DMA传输，中断响应等功能。
Realize the interface between PCI9054 and the PCI bus, including the bus arbitration, read and write of the registers, the configuration of the EEPROM, the DMA transfer, interrupt response and so on.
研究了智能分站的硬件和软件结构，详细分析了RS- 485总线通讯技术、双端口ram仲裁技术。
It studies the intelligent sub-station about its hardware and software structure, detailedly analyses RS-485 bus communication technique and bi-port RAM arbitration technique.
最大优点就是利用CAN总线非破坏性仲裁技术优先处理主要的故障，实现了更高的智能水平。
The biggest advantage is the use of CAN bus technology, non-destructive arbitration priority major failure to achieve a high level of intelligence.
CAN具有优先权和仲裁功能，多个单片机可通过CAN控制器连接到CAN总线上，形成多主机的局部控制网。
Can also functions as bus access priority and arbitration. Several single chip microcomputers can be connected to can bus through can controller to form a multi-master area controller network.
它具有仲裁开销小，扩展性好，各模块公平占用总线等特点。
It specifies in low arbitration overhead, fine scalability, fair utilization by all masters, etc.
当仲裁器发现有总线请求进入时，就在总线应答线上发送应答信号。
When the arbiter sees a bus request come in, it sends its reply on the bus grant line.
该总线桥是某型协调控制器系统的通讯核心，实现了系统下层的背板总线、背板总线管理器与上位机epp并口之间的协议转换以及通讯仲裁功能。
This bridge is the core of communication of the controller system, it connects the bottom level backplane bus, backplane bus controller, and PC EPP parallel port.
该总线桥是某型协调控制器系统的通讯核心，实现了系统下层的背板总线、背板总线管理器与上位机epp并口之间的协议转换以及通讯仲裁功能。
This bridge is the core of communication of the controller system, it connects the bottom level backplane bus, backplane bus controller, and PC EPP parallel port.
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